-- ***********************************************************************
--
-- DESCRIPTION
--
--   Adder 8 bits component.
-- 
-- REQUIRED COMPONENTS
--
--   Full Adder (fa.vhd).
--
-- PORTS
--
--   (I)  A:     Data-In (8 bits)
--   (I)  B:     Data-In (8 bits)
--	 (I)  Cin:   Carry In (1 bit)
--   (O)  S:     Data-Out (8 bits)
--	 (O)  Cout:  Carry Out (1 bit)
--
-- AUTHORS
--
--   14.12.2001 - Xavier Perseguers & Tadeusz Senn
--
-- ***********************************************************************

-- Declarations ----------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

-- Entity ----------------------------------------------------------------

entity Adder_8 is
	port (A, B : in std_logic_vector(7 downto 0);
		  Cin : in std_logic;
		  S : out std_logic_vector(7 downto 0);
		  Cout : out std_logic);
end Adder_8;

-- Architecture ----------------------------------------------------------

architecture structural of Adder_8 is

	component FA
		port (A, B, Cin: in std_logic;
		      S, Cout: out std_logic);
	end component;

	signal T1, T2, T3, T4, T5, T6, T7: std_logic;

begin

	F0: FA port map (A(0), B(0), Cin, S(0), T1);
	F1: FA port map (A(1), B(1), T1, S(1), T2);
	F2: FA port map (A(2), B(2), T2, S(2), T3);
	F3: FA port map (A(3), B(3), T3, S(3), T4);
	F4: FA port map (A(4), B(4), T4, S(4), T5);
	F5: FA port map (A(5), B(5), T5, S(5), T6);
	F6: FA port map (A(6), B(6), T6, S(6), T7);
	F7: FA port map (A(7), B(7), T7, S(7), Cout);

end structural;