-- ***********************************************************************
--
-- DESCRIPTION
--
--   ALU 1 bit component.
-- 
-- REQUIRED COMPONENTS
--
--   Full Adder (fa.vhd)
--
-- PORTS
--
--   (I)  A:         A input (1 bit)
--   (I)  B:         B input (1 bit)
--   (I)  Cin:       Input carry (1 bit)
--   (I)  ALUCtrl:   Function selection (3 bits)
--   (O)  R:         Result (1 bit)
--   (O)  Cout:      Output carry (1 bit)
--
-- AUTHORS
--
--   09.11.2001 - Xavier Perseguers & Tadeusz Senn
--
-- ***********************************************************************

-- Declarations ----------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

-- Entity ----------------------------------------------------------------

entity alu1 is
	port (A, B, Cin : in std_logic;
	      Op : in std_logic_vector (2 downto 0);
	      R, Cout : out std_logic);
end alu1;

-- Architecture ----------------------------------------------------------

architecture comportemental of alu1 is

signal Tr, Tout, Binv : std_logic;

component FA
	port(A, B, Cin: in std_logic;
	     S, Cout: out std_logic);
end component;

begin

C1: FA port map (A, Binv, Cin, Tr, Tout);

	process (B, Cin, Op)
	begin
		if (Op(2) = '1') then
			Binv <= not B;
		else
			Binv <= B;
		end if;
	end process;

	process (A, Binv, Cin, Tr, Tout, Op)
	begin
		case Op is
			when "000" =>  R <= A AND Binv;
				       Cout <= '0';
			when "001" =>  R <= A OR Binv;
				       Cout <= '0';
			when "010" =>  R <= Tr;
				       Cout <= Tout;
			when "110" =>  R <= Tr;
				       Cout <= Tout;
			when others => R <= 'X';
				       Cout <= 'X';
		end case;	
	end process;

end comportemental;