-- ***********************************************************************
--
-- DESCRIPTION
--
--   ALU 32 bits component.
-- 
-- REQUIRED COMPONENTS
--
--   ALU 1 bit (alu1.vhd)
--
-- PORTS
--
--   (I)  A:         A input (32 bits)
--   (I)  B:         B input (32 bits)
--   (I)  Cin:       Input carry (1 bit)
--   (I)  ALUCtrl:   Function selection (3 bits)
--   (O)  R:         Result (32 bits)
--   (O)  Cout:      Output carry (1 bit)
--
-- AUTHORS
--
--   09.11.2001 - Xavier Perseguers & Tadeusz Senn
--
-- ***********************************************************************

-- Declarations ----------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

-- Entity ----------------------------------------------------------------

entity alu32 is
	port (A, B: in std_logic_vector (31 downto 0);
	      Cin : in std_logic;
	      Op : in std_logic_vector (2 downto 0);
	      R : out std_logic_vector (31 downto 0); 
	      Cout, Z, V : out std_logic);
end alu32;

-- Architecture ----------------------------------------------------------

architecture structural of alu32 is

signal TC, TR : std_logic_vector (31 downto 0);
signal TCin : std_logic;

component Alu1
	port(A, B, Cin : in std_logic;
	     Op : in std_logic_vector (2 downto 0);
	     R, Cout : out std_logic);
end component;

begin

G: for i in 1 to 31 generate
	Axx : Alu1 port map(A(i), B(i), TC(i - 1), Op, TR(i), TC(i));
end generate;

A00 : Alu1 port map(A(00), B(00), TCin, Op, TR(00), TC(00));

process (Cin, Op)
begin
	if (Op(2) = '1') then
		TCin <= '1';
	else
		TCin <= Cin;
	end if;
end process;

process (TR, A, B, Op)
begin
	R <= TR;
	Cout <= TC(31);
	
	Z <= '1' when TR = X"00000000" else '0';
	
	case Op is
		when "010" =>  V <= ((not A(31)) and (not B(31)) and TR(31)) or (A(31) and B(31) and (not TR(31)));
		when "110" =>  V <= ((not A(31)) and B(31) and TR(31)) or (A(31) and (not B(31)) and (not TR(31)));
		when others => V <= '0';
	end case;

end process;

end structural;