library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity fa is
	port(A, B, Cin: in std_logic;
	     S, Cout: out std_logic);
end fa;

architecture synth of fa is
begin
	S <= A xor B xor Cin;
	Cout <= (A and B) or (Cin and (A xor B));
end synth;