-- ***********************************************************************
--
-- DESCRIPTION
--
--   Memory 4x 4 bits.
-- 
-- REQUIRED COMPONENTS
--
--   None.
--
-- PORTS
--
--   (I)  Adr:       Address (2 bits)
--   (I)  D_in:      Input Data (4 bits)
--   (I)  CS:        Component Selection (1 bit)
--   (I)  OE:        Output Enabled (1 bit)
--   (I)  WE:        Write Enabled (1 bit)
--   (O)  D_out:     Output Data (4 bits)
--
-- AUTHORS
--
--   23.11.2001 - Xavier Perseguers & Tadeusz Senn
--
-- ***********************************************************************

-- Declarations ----------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

-- Entity ----------------------------------------------------------------

entity Mem4x4 is
    port (Adr: in std_logic_vector (1 downto 0);
    	  D_in: in std_logic_vector (3 downto 0);
	  CS, OE, WE: in std_logic;
	  D_out: out std_logic_vector (3 downto 0));
		  
end Mem;

-- Architecture ----------------------------------------------------------

architecture comportemental of Mem4x4 is

begin

	memory: process (Adr, CS, OE, WE, D_in)

		type mem_addr is array (3 downto 0) of std_logic_vector(3 downto 0);
		variable memory_a : mem_addr;

	begin
		
		if CS = '1' then
			
			if WE = '1' then 
			
				memory_a (conv_integer(Adr)):= D_in;

				D_out <= (others => 'Z');
			
			else
			
				if OE = '1' then
				
					D_out <= memory_a(conv_integer(Adr));
				
				else
					
					D_out <= (others => 'Z');
					
				end if;
			
			end if;
			
		else
		
			D_out <= (others => 'Z');
			
		end if;
		
	end process memory;

end comportemental;