-- ***********************************************************************
--
-- DESCRIPTION
--
--   MULTIPLIER 8 bits component (combinatory).
-- 
-- REQUIRED COMPONENTS
--
--   Multiplier 8 bits stage (multiplier_8_stage.vhd)
--
-- PORTS
--
--   (I)  X:         X input (8 bits)
--   (I)  Y:         Y input (8 bits)
--   (O)  Z:         Result (16 bits)
--
-- AUTHORS
--
--   14.12.2001 - Xavier Perseguers & Tadeusz Senn
--
-- ***********************************************************************

-- Declarations ----------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

-- Entity ----------------------------------------------------------------

entity Multiplier_8 is
	port (X, Y : in std_logic_vector(7 downto 0);
		  Z : out std_logic_vector(15 downto 0));
end Multiplier_8;

-- Architecture ----------------------------------------------------------

architecture structurale of Multiplier_8 is

	component Multiplier_8_stage
		port (X, Y : in std_logic_vector(7 downto 0);
			  Z : out std_logic_vector(7 downto 0);
			  Cout : out std_logic);
	end component;
	
	signal S1, S2, S3, S4 : std_logic_vector(7 downto 0);
	signal S5, S6, S7     : std_logic_vector(7 downto 0);

	signal C1, C2, C3, C4 : std_logic;
	signal C5, C6, C7     : std_logic;

	signal P0, P1, P2, P3 : std_logic;
	signal P4, P5, P6     : std_logic;
	
	signal KZero : std_logic;
	
	signal  PP1,  PP2,  PP3 : std_logic_vector(7 downto 0);
	signal  PP4,  PP5,  PP6 : std_logic_vector(7 downto 0);
	signal  PP7,  PP8,  PP9 : std_logic_vector(7 downto 0);
	signal PP10, PP11, PP12 : std_logic_vector(7 downto 0);
	signal PP13, PP14       : std_logic_vector(7 downto 0);
	
begin -- structurale

	KZero <= '0';

	PP1 <= (Y(1) And X(7),
		 	Y(1) And X(6),
		 	Y(1) And X(5),
		 	Y(1) And X(4),
		 	Y(1) And X(3),
		 	Y(1) And X(2),
		 	Y(1) And X(1),
		 	Y(1) And X(0));

	PP2 <= (KZero,
		 	Y(0) And X(7),
		 	Y(0) And X(6),
		 	Y(0) And X(5),
			Y(0) And X(4),
			Y(0) And X(3),
			Y(0) And X(2),
			Y(0) And X(1));

	PP3 <= (Y(2) And X(7),
			Y(2) And X(6),
			Y(2) And X(5),
			Y(2) And X(4),
			Y(2) And X(3),
			Y(2) And X(2),
			Y(2) And X(1),
			Y(2) And X(0));

	PP4 <= C1 & S1(7 downto 1);

	PP5 <= (Y(3) And X(7),
			Y(3) And X(6),
			Y(3) And X(5),
			Y(3) And X(4),
			Y(3) And X(3),
			Y(3) And X(2),
			Y(3) And X(1),
			Y(3) And X(0));

	PP6 <= C2 & S2(7 downto 1);

	PP7 <= (Y(4) And X(7),
			Y(4) And X(6),
			Y(4) And X(5),
			Y(4) And X(4),
			Y(4) And X(3),
			Y(4) And X(2),
			Y(4) And X(1),
			Y(4) And X(0));

	PP8 <= C3 & S3(7 downto 1);
	
	PP9 <= (Y(5) And X(7),
			Y(5) And X(6),
			Y(5) And X(5),
			Y(5) And X(4),
			Y(5) And X(3),
			Y(5) And X(2),
			Y(5) And X(1),
			Y(5) And X(0));
	
	PP10 <= C4 & S4(7 downto 1);
	
	PP11 <= (Y(6) And X(7),
			Y(6) And X(6),
			Y(6) And X(5),
			Y(6) And X(4),
			Y(6) And X(3),
			Y(6) And X(2),
			Y(6) And X(1),
			Y(6) And X(0));
	
	PP12 <= C5 & S5(7 downto 1);
	
	PP13 <= (Y(7) And X(7),
			Y(7) And X(6),
			Y(7) And X(5),
			Y(7) And X(4),
			Y(7) And X(3),
			Y(7) And X(2),
			Y(7) And X(1),
			Y(7) And X(0));
	
	PP14 <=	C6 & S6(7 downto 1); 
	
	
	M1 : Multiplier_8_stage port map (PP1, PP2,	S1, C1);
	M2 : Multiplier_8_stage port map (PP3, PP4,	S2, C2);
	M3 : Multiplier_8_stage port map (PP5, PP6, S3, C3);
	M4 : Multiplier_8_stage port map (PP7, PP8, S4, C4);
	M5 : Multiplier_8_stage port map (PP9, PP10, S5, C5);
	M6 : Multiplier_8_stage port map (PP11, PP12, S6, C6);
	M7 : Multiplier_8_stage port map (PP13, PP14, S7, C7);
	
	P0 <= Y(0) And X(0);
	P1 <= S1(0);
	P2 <= S2(0);
	P3 <= S3(0);
	P4 <= S4(0);
	P5 <= S5(0);
	P6 <= S6(0);
		
	Z <= C7 & S7 & (P6, P5, P4, P3, P2, P1, P0);
	
end structurale;