-- ***********************************************************************
--
-- DESCRIPTION
--
--   MULTIPLIER 8 bits component: one stage of 8 bits.
-- 
-- REQUIRED COMPONENTS
--
--   Full Adder (fa.vhd)
--
-- PORTS
--
--   (I)  X:         X input (8 bits)
--   (I)  Y:         Y input (8 bits)
--   (O)  Z:         Z output (8 bits)
--   (O)  Cout:      carry out (1 bit)
--
-- AUTHORS
--
--   14.12.2001 - Xavier Perseguers & Tadeusz Senn
--
-- ***********************************************************************

-- Declarations ----------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

-- Entity ----------------------------------------------------------------

entity multiplier_8_stage is
	port (X, Y: in std_logic_vector (7 downto 0);
		  Z: out std_logic_vector (7 downto 0);
		  Cout: out std_logic);
end multiplier_8_stage;

-- Architecture ----------------------------------------------------------

architecture structural of multiplier_8_stage is
	
	component fa
		port (A, B, Cin: in std_logic;
		      S, Cout: out std_logic);
	end component;

	signal KZero: std_logic;
	signal T1, T2, T3, T4, T5, T6, T7: std_logic;

begin
	
	KZero <= '0';

	F0: FA port map (X(0), Y(0), KZero, Z(0), T1);
	F1: FA port map (X(1), Y(1), T1, Z(1), T2);
	F2: FA port map (X(2), Y(2), T2, Z(2), T3);
	F3: FA port map (X(3), Y(3), T3, Z(3), T4);
	F4: FA port map (X(4), Y(4), T4, Z(4), T5);
	F5: FA port map (X(5), Y(5), T5, Z(5), T6);
	F6: FA port map (X(6), Y(6), T6, Z(6), T7);
	F7: FA port map (X(7), Y(7), T7, Z(7), Cout);

end structural;