-- ***********************************************************************
--
-- DESCRIPTION
--
--   MULTIPLIER 8 bits component (sequential).
-- 
-- REQUIRED COMPONENTS
--
--   Multiplier 8 bits stage (multiplier_8_stage.vhd)
--
-- PORTS
--
--   (I)  X:         Input #1 (8 bits)
--   (I)  Y:         Input #2 (8 bits)
--   (I)  Clk:       Clock (1 bit)
--   (I)  Reset:     Reset (1 bit)
--   (I)  Start:     Start (1 bit)
--   (O)  Z:         Result (16 bits)
--   (O)  Done:      Result is valid (1 bit)
--
-- AUTHORS
--
--   14.12.2001 - Xavier Perseguers & Tadeusz Senn
--   11.01.2002 - Xavier Perseguers & Tadeusz Senn
--
-- ***********************************************************************

-- Declarations ----------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

-- Entity ----------------------------------------------------------------

entity Multiplier_8x8 is
	port (X, Y : in std_logic_vector(7 downto 0);
		  Clk, Reset, Start : in std_logic;
		  Z : out std_logic_vector(15 downto 0);
		  Done : out std_logic);
end Multiplier_8x8;

-- Architecture ----------------------------------------------------------

architecture structurale of Multiplier_8x8 is

	component multiplier_internal
		port (Multiplier, Multiplicand: in std_logic_vector (7 downto 0);
			  Clk, Load_Multiplicand, Load_Multiplier, Shift_Multiplier,
			  Reset_Product, Load_Product, Shift_Product: in std_logic;
			  Product: out std_logic_vector (15 downto 0));
	end component;
	
	component controller
		port (Start, Reset, Clk: in std_logic;
			  Done, Load_Multiplicand, Load_Multiplier, Shift_Multiplier,
			  Reset_Product, Load_Product, Shift_Product: out std_logic);
	end component;

	signal T0, T1, T2, T3, T4, T5: std_logic;

begin -- Multiplier_8x8

	MI: multiplier_internal port map (  Multiplier => X,
										Multiplicand => Y,
										Clk => Clk,
										Load_Multiplicand => T0,
										Load_Multiplier => T1,
										Shift_Multiplier => T2,
										Reset_Product => T3,
										Load_Product => T4,
										Shift_Product => T5,
										Product => Z);
										
	C: controller port map (Start => Start,
							Reset => Reset,
							Clk => Clk,
							Done => Done,
							Load_Multiplicand => T0,
							Load_Multiplier => T1,
							Shift_Multiplier => T2,
							Reset_Product => T3,
							Load_Product => T4,
							Shift_Product => T5);

end structurale;