-- ***********************************************************************
--
-- DESCRIPTION
--
--   Internal structure of MULTIPLIER.
-- 
-- REQUIRED COMPONENTS
--
--   Multiplier 8 bits (piso_register.vhd)
--	 Multiplicand 8 bits (pipo_register.vhd)
--   Full Adder 8 bits (adder_8.vhd)
--	 Product Register (product_register.vhd)
--
-- PORTS
--
--   (I)  Multiplier:     	  Multiplier (8 bits)
--   (I)  Multiplicand:       Multiplicand (8 bits)
--   (I)  Clk:       		  Clock (1 bit)
--   (I)  Load_Multiplicand:  Load Multiplicand (1 bit)
--   (I)  Load_Multiplier:    Load Multiplier (1 bit)
--   (I)  Shift_Multiplier:   Shift Multiplier (1 bit)
--   (I)  Reset_Product:      Reset Product Register (1 bit)
--   (I)  Load_Product:       Load Product Register (1 bit)
--   (I)  Shift_Product:      Shift Product Register (1 bit)
--   (O)  Product:			  Product (16 bits)
--
-- AUTHORS
--
--   14.12.2001 - Xavier Perseguers & Tadeusz Senn
--
-- ***********************************************************************

-- Declarations ----------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

-- Entity ----------------------------------------------------------------

entity multiplier_internal is
	port (Multiplier, Multiplicand: in std_logic_vector (7 downto 0);
		  Clk, Load_Multiplicand, Load_Multiplier, Shift_Multiplier,
		  Reset_Product, Load_Product, Shift_Product: in std_logic;
		  Product: out std_logic_vector (15 downto 0));
end multiplier_internal;

-- Architecture ----------------------------------------------------------

architecture structural of multiplier_internal is
	
	component PISO_Register
		port (Data_In : in std_logic_vector(7 downto 0);
			  Clk, Load, Shift_Right : in std_logic;
			  Data_Out : out std_logic);
	end component;

	component PIPO_Register
		port (Data_In : in std_logic_vector(7 downto 0);
			  Clk, Load : in std_logic;
			  Data_Out : out std_logic_vector(7 downto 0));
	end component;
	
	component Adder_8 
		port (A, B : in std_logic_vector(7 downto 0);
			  Cin : in std_logic;
			  S : out std_logic_vector(7 downto 0);
			  Cout : out std_logic);
	end component;
	
	component Product_Register
		port (Product_In : in std_logic_vector(8 downto 0);
			  Clk, Reset, Load, Shift_Right : in std_logic;
			  Product_Out : out std_logic_vector(16 downto 0));
	end component;
	
	signal Multiplier_Out : std_logic;
	signal Multiplicand_Out : std_logic_vector (7 downto 0);
	signal Multiplier_Out_8 : std_logic_vector (7 downto 0);
	signal AND_Out : std_logic_vector (7 downto 0);
	signal Product_In : std_logic_vector (16 downto 8); -- 9 bits
	signal Product_Out : std_logic_vector (16 downto 0); -- 17 bits
	signal KZero : std_logic;
	
begin -- structural

	KZero <= '0';

	PS: PISO_Register port map (Multiplier, Clk, Load_Multiplier, 
								Shift_Multiplier, Multiplier_Out);
	
	PP: PIPO_Register port map (Multiplicand, Clk, Load_Multiplicand,
								Multiplicand_Out);
								
	Multiplier_Out_8 <= (others => Multiplier_Out);
	
	AND_Out <= Multiplier_Out_8 and Multiplicand_Out;
	
	A:  Adder_8 port map (AND_Out, Product_Out(15 downto 8), KZero, 
						  Product_In(15 downto 8), Product_In(16));
	
	PR: Product_Register port map (Product_In, Clk, Reset_Product, Load_Product, 
								   Shift_Product, Product_Out);
								   
	Product <= Product_Out (15 downto 0);
	
end structural;