-- ***********************************************************************
--
-- DESCRIPTION
--
--   PIPO Register (Parallel In - Parallel Out) component.
-- 
-- REQUIRED COMPONENTS
--
--   None.
--
-- PORTS
--
--   (I)  Data_In:     Parallel Data-In (8 bits)
--   (I)  Clk:         Clock (1 bit)
--   (I)  Load:        Load (1 bit)
--   (O)  Data_Out:    Parallel Data-Out (1 bit)
--
-- AUTHORS
--
--   14.12.2001 - Xavier Perseguers & Tadeusz Senn
--
-- ***********************************************************************

-- Declarations ----------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

-- Entity ----------------------------------------------------------------

entity PIPO_Register is
	port (Data_In : in std_logic_vector(7 downto 0);
		  Clk, Load : in std_logic;
		  Data_Out : out std_logic_vector(7 downto 0));
end PIPO_Register;

-- Architecture ----------------------------------------------------------

architecture comportemental of PIPO_Register is
	signal sData : std_logic_vector (7 downto 0);
begin

	Data_Out <= sData;
	
	process (Clk)
	begin
	
		if (Clk'event and Clk = '1') then
			if (Load = '1') then
				sData <= Data_In;
			end if;
		end if;
		
	end process;
	
end comportemental;