-- ***********************************************************************
--
-- DESCRIPTION
--
--   Register file.
-- 
-- REQUIRED COMPONENTS
--
--   none
--
-- PORTS
--
--   (I)  aa:        Address for Output #1 (3 bits)
--   (I)  ab:        Address for Output #2 (3 bits)
--   (I)  aw:        Write Address (3 bits)
--   (I)  clk:       Clock
--   (I)  WData:     Data to be written (32 bits)
--   (O)  a:         Output #1 (32 bits)
--   (O)  b:         Output #2 (32 bits)
--
-- AUTHORS
--
--   23.11.2001 - Xavier Perseguers & Tadeusz Senn
--
-- ***********************************************************************

-- Declarations ----------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

-- Entity ----------------------------------------------------------------

entity RF is
    port (aa, ab, aw : 	in std_logic_vector(2 downto 0);
	  clk :	in std_logic;
	  WData : in std_logic_vector (31 downto 0);
	  RegWrite : in std_logic;
	  a, b : out std_logic_vector(31 downto 0));
end RF;

-- Architecture ----------------------------------------------------------

architecture comportemental of RF is

begin

	reg_file: process (aa, ab, clk, RegWrite, aw)

		type rf_addr is array(7 downto 0) of std_logic_vector(31 downto 0);
		variable register_file_a : rf_addr;

	begin
		
		a <= register_file_a(conv_integer(aa));
		b <= register_file_a(conv_integer(ab));
	
		register_file_a(0) := (others => '0');		
			
		if clk'event and clk = '1' then
			if RegWrite = '1' and aw /= "000" then
				register_file_a(conv_integer(aw)) := WData;
			end if;
		end if;

	end process reg_file;

end comportemental;